The present invention relates in general to switched capacitor circuits and in particular to analog to digital conversion circuits, systems and methods with gain scaling switched-capacitor array.
One particular technique for performing analog to digital (A/D) conversion is through successive approximation. The basic successive approximation A/D converter (ADC) includes an analog comparator and a clocked feedback loop having a successive approximation register (SAR) and a digital to analog converter (DAC).
Generally, the analog input signal voltage is sampled onto an array of weighted capacitors, during the sampling phase, the top plates of which are coupled to one comparator input. The other comparator input is coupled to a comparison voltage, which could be a fixed reference voltage in a single-ended system or the voltage at the top plates of second capacitor array in a differential system.
During the first clock cycle of the subsequent conversion phase, the bottom plate of the capacitor representing the digital most significant bit (MSB) is coupled to a reference voltage while the bottom plates of the remaining capacitors in the array are coupled to ground or a second reference voltage (ground will be assumed here). The new top plate voltage appears at the input of the comparator and is compared against the comparison voltage. The new top plate voltage is a scaled version of       [                  Voef        2            -      ain        ]    ·  k
where k is the ratio of capacitors. The sign of this quantity is the factor of interest. If the new top plate voltage is below the comparison voltage, then the MSB is xe2x80x9ckeptxe2x80x9d by the SAR in the feedback loop by maintaining its bottom plate coupled to the reference voltage. On the other hand, if the top plate voltage is above the comparison voltage, the SAR couples and the bottom plate of the MSB capacitor to ground. The state of the MSB capacitor represents the MSB of the digital output word as a Logic 1. The bottom plate of the second MSB is then coupled to the reference voltage and the same test is performed to determine the state of the next digital code bit. The successive approximation algorithm continues by repeating this procedure for the remaining capacitors in the array such that the voltage difference at the inputs to the comparator converge to zero. At the end of this bit cycling process, the configuration of the switches coupling the bottom plates either to Vref or Gnd represents the input sample in digital form.
Successive approximation A/D converters are useful a wide range of applications, including data acquisition, test equipment, instrumentation, cellular communications, among others. Notwithstanding, in order to improve and broaden the utility of this type of A/D converter, significant challenges remain to be addressed. These challenges include improving the device speed given a set of process constraints, reducing the coding error rate, handling metastable states and calibration of the DAC.
The principles of the present invention are embodied in circuits and methods for gain scaling in charge redistribution analog to digital converters. According to one such embodiment, a method of gain scaling is disclosed which includes the step of segmenting a bit weighted capacitor array into a first segment having at least one capacitor representing least significant bit and a second segment having at least one capacitor representing most significant bit. During a sampling phase, an input signal is sampled onto the at least one capacitor of the second segment while the at least one capacitor of the first segment is coupled to a fixed voltage.
The inventive principles are also embodied in an analog to digital converter including a comparator, an array of capacitors coupled to an input of the comparator, and switching circuitry for controlling the voltages stored on the array of capacitors. In particular, the array of capacitors is segmented into a first segment of capacitors representing most significant bits and a second segment of capacitors representing least significant bits. The switching circuitry during a sampling phase selectively couples the capacitors of the first segment to an analog input of the converter and the capacitors of the second segment to a fixed voltage.
Among the advantages obtained through application of the inventive principles, is a substantial reduction in the amount of parasitic capacitance which must be charged or discharged during the sampling phase. This allows the analog to digital converter to operate at higher sampling rates and improves the operational linearity.